1. Field of the Invention
The present invention relates to an analog/digital hybrid masterslice integrated circuit, and more particularly to a Bi-CMOS analog/digital hybrid IC with a level-shift circuit fixedly built-in in a masterwafer substrate as a hard-macro block.
2. Description of the Related Art
Recently, analog/digital hybrid masterslice ICs to which the present invention relates have become more advanced as it has become possible to integrate on the same chip various large scale high precision analog circuits and large scale digital logic circuits in accordance with the advancement of a Bi-CMOS process. Conventionally, a method for developing analog/digital hybrid LSIs whereby an analog circuit is designed by hand, a digital circuit is designed using a cell base method and both are then integrated onto the same chip has been widely adopted. However, although this method allows variations in designs, the development period is fairly long and the development cost inevitably becomes expensive.
As a method intended to compensate for the above weak points in analog/digital hybrid LSIs, there has been proposed and developed a so-called fixed substrate type analog/digital hybrid masterwafer method of the kind to which the present invention relates. In that method an analog master section formed by arranging electronic components such as transistors, resistors and capacitors in array form and a gate array (G/A) section are constructed on the same chip. This has considerably improved both the development period and the development cost.
The CMOS logic section usually adopts a power supply voltage of 5 V. On the other hand, for the bipolar circuits and the CMOS analog circuits, power supply voltages of above 5 V, for example, 5 V, 9 V, 12 V are widely used.
If the cell base method is used, a well designed circuit can be attained by selecting a suitable process fitted to the power supply voltage and by adjusting the device parameters. However, there is a great design restriction in the fixed substrate type masterwafer. For example, if the power supply voltage for the bipolar analog circuit is 10 V and a MOS transistor is used to control the base current of an NPN bipolar transistor, a 5 V.sub.Peak-Peak pulse signal generated in the MOS logic circuit as it is will not be sufficient to drive the MOS transistor, and it will be necessary to increase the amplitude thereof to 10 V.sub.P-P in order to drive the transistor. To this end, a level conversion circuit is assumed to be constructed by bipolar elements, the 5 V.sub.P-P control signal generated in the MOS logic circuit is increased by the bipolar device to a voltage of 10 V.sub.P-P, and can then turn-ON and -OFF the MOS transistors arranged at both ends of the bipolar device. Furthermore, it is then returned to the bipolar analog circuit section. Accordingly, as there is a high voltage pulse signal including higher harmonics going backwards and forwards right above the analog circuit section, this will be a cause for the digital signal to be mixed into the analog circuit as noise.